1. Field of the Invention
The present invention relates to a flash memory which is a nonvolatile memory, more particularly to a flash memory system provided with a management system for appropriately managing a flash memory.
2. Discussion of the Background
As a storage medium for use in a computer system, a magnetic recording medium such as a hard disc or a floppy disc has been heretofore used. Above all, the hard disc having a large capacity and capable of operating at a high speed can store a large amount of data, and therefore it is positioned as a central storage medium of the system.
However, the manufacturing process of the hard disc is complicated, and it is difficult to realize its miniaturization, weight-saving and cost reduction. Since a structure is moved during the use of the hard disc, a relatively large consumption power is required, and particularly in the case that the hard disc is applied to a portable apparatus or the like, this problem tends to rise.
As the storage medium other than the hard disc, a flash memory is known as a nonvolatile storage element. In the flash memory, a power supply to maintain storage is unnecessary, and the miniaturization and the weight-saving are possible.
The flash memory, for structural reasons thereof, has a finite physical life of about 1010 in terms of an rewriting times. Therefore, in order to use the flash memory relatively safely and stably for a long period of time, an expired storage element and a section in which a defect occurs are detected, and these troubles need to be avoided to store data. Furthermore, in the case of the flash memory, new data cannot be written over a section in which data has already been stored. Therefore, when the new data is to be stored, a stored area must be once erased before the data is written. However, a unit which can be erased is not an individual storage element (=bit) unit, but it is a block unit such as 4 kilobytes or 8 kilobytes. Therefore, generally, after a data portion other than the data to be rewritten is taken out of the block to be erased, the block is erased, and the data portion needs to be newly added/written again.
In Japanese Patent Application Laid-open No. 292798/1990, a flash EEprom system is described for the purpose of enhancing a writing/reading speed to a flash memory and managing a defective cell and the like. In the flash EEprom system described therein, an access time is intended to be enhanced using a cache memory. However, shortening of the access time dependent on the cache memory is naturally limited, and in order to further enhance the writing/reading speed to the flash memory, an operation speed of the entire flash memory system needs to be enhanced.
Moreover, in the above-described publication, for the management of the defective cell and the like, a redundant portion is provided with ECC and another information, and replacement bit, replacement sector and another information, and the defective cell and the like are managed only with the information of the redundant portion. However, since the defective cell and the like are managed only with the redundant portion, the storage capacity of the redundant portion has to be enlarged, which diminishes an area to store actual data. Furthermore, since the system manages the defective cell and the like only with the redundant portion, before reading the actual data, the redundant data is read, and a propriety of data stored in the memory is judged or recovery or the like of the data is performed, which remarkably delays the access time.
Additionally, the flash memory system is a nonvolatile memory, but during turning-on of a power supply or during resetting, for a controller to grasp a content and state of the flash memory, the content of the flash memory, especially the redundant data needs to be read. However, as described above, the reading speed of the flash memory is slower as compared with ordinary RAM or the like, much time is therefore required to grasp all information, and as a result, the system becomes slow in starting.
Such delay in rising is a fatal problem, for example, for a digital camera or another system which needs to be instantly ready for operation after power is turned on, and a flash memory system which can be started at a higher speed has been demanded.
An object of the present invention is to realize a flash memory system which is fast in rising speed during turning-on of a power supply or after resetting, has little delay in writing/reading time, can relatively easily perform a writing operation, can realize a high-speed operation and which can adequately manage a defective sector, defective bit or the like.
The present inventors have extended researches to enhance a writing/reading speed to the flash memory, and as a result, have proposed an address conversion table. The address conversion table formed on S-RAM or another storage medium which is accessible at a high speed correlates a logical address designated by a host computer side with an actual address of the flash memory or physical address, and mutually converts the addresses.
The address conversion table is also defined for each block as a minimum erasing unit of the flash memory, and the above-described addresses are treated as a logical block address and a physical block address, respectively. In this manner, by performing address conversion for each block corresponding to the minimum erasing unit, the management of the flash memory particularly in the writing operation is facilitated, and the writing operation can be performed at a high speed.
Moreover, an area of the logical address and an area of the physical address differ in size, and the logical address area is set smaller than the physical address area. By such setting, a difference of both areas can be used as a spare area. Specifically, the spare area is used as a queue in an operation standby state, and changed with a defective block, or used as a substitute for an area in which new data is to be written during the writing operation. This further enhances the operation speed.
Furthermore, in addition to the address conversion table, there is provided a block status table which has, as data indicating a state of each physical block on the flash memory, data indicating at least whether or not the block is good, whether or not a bad sector is present and whether or not the block is used. Since the block status table is provided, without accessing the flash memory relatively slow in the operation speed, the state of each block in the flash memory can instantly be grasped, a defective block and defective sector can easily be managed, and the operation speed is further enhanced.
Additionally, the address conversion table, block status table, queue and another internal information are usually formed on the storage medium (S-RAM) which is accessible at a high speed. However, since such storage medium is volatile, during cutting-off of power supply or during resetting, the medium is extinguished, or reliability is lost. Therefore, the storage data, i.e., the above-described internal information needs to be stored on the nonvolatile storage medium or flash memory. Then, during turning-on of the power supply or during resetting, the flash memory is accessed, and the address conversion table, block status table, queue and another internal information are restored to a previous state by the stored data.
However, the internal information changes every time the writing/reading operation to the flash memory is performed, but if every information is stored, an enormous storage area becomes necessary. Moreover, to perform such operation for each writing/reading, the longer time the storing takes, the more time is wasted, and as a result, the operation speed is decelerated. Furthermore, if during the turning-on of the power supply or during resetting all areas of the flash memory are accessed, and the address conversion table, block status table, queue and another internal information are restored, an enormous time further becomes necessary, and a system becomes very slow in rising.
To solve the problem, it is convenient to store these internal information data collectively in such a manner that they can instantly be read. Moreover, for a content to be stored, initial value+xcex1 record, i.e., all data only of the initial value are stored, and for subsequently generated changes, only data of the change (xcex94 record) is stored. Then, the data capacity can be reduced, and the access time can considerably be shortened. Moreover, in this case, by also recording error correction code data indicating a position and size of a trouble occurring in the xcex94 record, data reliability is significantly enhanced. Additionally, during the turning-on of the power supply or during resetting these data can be used to restore the previous state.
Specifically, the above-described object is attained by the following constitutions.
(1) A flash memory system comprising a memory manager for managing data transmission/reception between a host computer and a flash memory, wherein
said memory manager mutually converts a logical address in which the flash memory is accessible from said host computer, and a physical address as an actual address of the flash memory,
said memory manager stores a change of internal information as xcex94 record in said flash memory, and
said memory manager, after resetting, restores an internal state to a state before the resetting by information of said xcex94 record.
(2) The flash memory system according to the above (1) wherein said xcex94 record is successively stored as data indicative of subsequent changes with respect to an initial value of the internal information to restore the internal information after the resetting.
(3) The flash memory system according to the above (1) or (2) wherein said xcex94 record has error correction code data.
(4) The flash memory system of any one of the above (1) to (3) wherein said xcex94 record is continuously written to a predetermined storage area.
(5) The flash memory system according to any one of the above (1) to (4) wherein:
said memory manager sets a size of an area of said logical address to be smaller than a size of an area of the physical address as the actual address of the flash memory, and
said memory manager has said xcex94 record in a surplus area of the physical address area which does not correspond to the logical address area.
(6) The flash memory system according to any one of the above (1) to (5) wherein said memory manager treats the physical address and the logical address every block divided corresponding to a minimum erasing unit of the flash memory.
(7) The flash memory system according to any one of the above (1) to (6) wherein:
said memory manager has an address conversion table for mutually converting a logical block address and a physical block address, and
this address conversion table and information of changes thereof are included in said xcex94 record.
(8) The flash memory system according to any one of the above (1) to (7) wherein:
said memory manager further has a block status table,
this block status table has data indicating a state of said physical block on the flash memory,
said data indicating at least whether or not the block is good, whether or not a bad sector is present and whether or not the block is used, and
the block status table and information of changes thereof are included in said xcex94 record.
(9) The flash memory system according to any one of the above (5) to (8) wherein:
said memory manager has a queue in a ready-to-use state in the surplus area of said physical address area not corresponding to the logical address area, and
information of this queue is included in said xcex94 record.
(10) The flash memory system according to any one of the above (1) to (9) wherein:
when data is written to the flash memory, said memory manager writes new data in a predetermined block in the queue, and
this data is set as the logical block address of an estimated writing destination, and an estimated writing destination block is set as the queue.
(11) The flash memory system according to any one of the above (1) to (10) wherein:
in a case where the estimated writing destination block has data other than data to be updated,
after transfer of a predetermined amount of data from the host computer is completed,
said memory manager transfers the existing data from the estimated writing destination block to the predetermined block in the queue in which the new data is written.
(12) The flash memory system according to any one of the above (1) to (11) wherein when a trouble occurs in an arbitrary block in the physical address area, said memory manager replaces the block with an arbitrary block in said queue.
(13) The flash memory system according to any one of the above (1) to (12) which is an IC chip.
(14) The flash memory system according to any one of the above (1) to (13) which is integral with the flash memory and is a card-shaped external storage system.